1. Field of the Invention
This invention relates to the improvement of a semiconductor device having bipolar transistors and MOS transistors formed therein.
2. Description of the Related Art
In recent years, the technique of miniaturizing MOS transistors in the field of integrated circuit technology using silicon has been further enhanced, and as a result, attempts have been made to lower the power source voltage V.sub.dd so as to attain the high reliability and low power consumption of the MOS transistors.
However, with an integrated circuit such as a totem-pole type BiCMOS gate having bipolar transistors and MOS transistors, the high-speed operation of the BiCMOS gate is deteriorated when the power source voltage V.sub.dd is lowered. The reason for this is considered to be that the built-in potential (voltage between the base and the emitter) V.sub.bi of the bipolar transistor is always kept physically constant and therefore the ratio (V.sub.bi /V.sub.dd) of the built-in potential V.sub.bi to the power source voltage V.sub.dd will become large.